View MAX1231_5422796.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1227/max1229/MAX1231 are serial 12-bit ana- log-to-digital converters (adcs) with an internal reference and an internal temperature sensor. these devices fea- ture an on-chip fifo, scan mode, internal clock mode, internal averaging, and autoshutdown?. the maximum sampling rate is 300ksps using an external clock. the MAX1231 has 16 input channels, the max1229 has 12 input channels, and the max1227 has 8 input channels. all input channels are configurable for single-ended or differential inputs in unipolar or bipolar mode. all three devices operate from a +3v supply and contain a 10mhz spi?-/qspi?-/microwire?-compatible serial port. the MAX1231 is available in 28-pin 5mm x 5mm tqfn with exposed pad and 24-pin qsop packages. the max1227/max1229 are only available in qsop pack- ages. all three devices are specified over the extended -40c to +85c temperature range. ________________________applications system supervision data-acquisition systems industrial control systems patient monitoring data logging instrumentation features internal temperature sensor (0.7c accuracy) 16-entry first-in/first-out (fifo) analog multiplexer with true differential track/hold 16-, 12-, 8-channel single ended 8-, 6-, 4-channel true differential (unipolar or bipolar) accuracy: 1 lsb inl, 1 lsb dnl, no missing codes overtemperature scan mode, internal averaging, and internal clock low-power single +3v operation 1ma at 300ksps internal 2.5v reference or external differential reference 10mhz 3-wire spi-/qspi-/microwire-compatible interface space-saving 28-pin 5mm x 5mm tqfn package max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ain0 top view eoc dout din cs sclk v dd gnd ref+ max1227 qsop ain1 ain2 ain5 ain3 ain4 ref-/ain6 cnvst/ain7 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 eoc dout din cs ain3 ain2 ain1 ain0 sclk v dd gnd ref+ ain7 ain6 ain5 ain4 12 11 9 10 cnvst/ain11 ref-/ain10 ain9 ain8 max1229 qsop + + pin configurations 19-2851; rev 7; 4/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package max1227 bcee+ 0c to +70c 16 qsop max1227beee+ -40c to +85c 16 qsop max1229 bcep+ 0c to +70c 20 qsop max1229beep+ -40c to +85c 20 qsop pin configurations continued at end of data sheet. ordering information continued at end of data sheet. autoshutdown is a trademark of maxim integrated products, inc. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad (tqfn only). connect to gnd.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +3.6v, f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v cs , sclk, din, eoc , dout to gnd.........-0.3v to (v dd + 0.3v) ain0Cain13, ref-/ain_, cnvst/ ain_, ref+ to gnd.........................................-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70c) 16-pin qsop (derate 8.3mw/c above +70c)...........667mw 20-pin qsop (derate 9.1mw/c above +70c)...........727mw 24-pin qsop (derate 9.5mw/c above +70c)...........762mw 28-pin tqfn 5mm x 5mm (derate 20.8mw/c above +70c) ........................1667mw operating temperature ranges max12__c__.......................................................0c to +70c max12__e__ ....................................................-40c to +85c storage temperature range .............................-60c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units dc accuracy (note 1) resolution res 12 bits integral nonlinearity inl 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1.0 lsb offset error 0.5 4.0 lsb gain error (note 2) 0.5 4.0 lsb offset error temperature coefficient 2 ppm/c fsr gain temperature coefficient 0.8 ppm/c channel-to-channel offset matching 0.1 lsb dynamic specifications (30khz sine wave input, 2.5v p-p , 300ksps, f sclk = 4.8mhz) signal-to-noise plus distortion sinad 71 db total harmonic distortion thd up to the 5th harmonic -80 dbc spurious-free dynamic range sfdr 81 dbc intermodulation distortion imd f in1 = 29.9khz, f in2 = 30.2khz 76 dbc full-power bandwidth -3db point 1 mhz full-linear bandwidth s/(n + d) > 68db 100 khz
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v, f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units conversion rate external reference 0.8 power-up time t pu internal reference (note 3) 65 s acquisition time t acq 0.6 s internally clocked 3.5 conversion time t conv externally clocked (note 4) 2.7 s externally clocked conversion 0.1 4.8 external clock frequency f sclk data i/o 10 mhz sclk duty cycle 40 60 % aperture delay 30 ns aperture jitter <50 ps analog input unipolar 0 v ref input voltage range bipolar (note 5) - v re f /2 v re f /2 v input leakage current v in = v dd 0.01 1 a input capacitance during acquisition time (note 6) 24 pf internal temperature sensor t a = +25 c 0.7 measurement error (note 7) t a = t min to t max 1.2 2.5 c tem p er atur e m easur em ent n oi se 0.4 c rms temperature resolution 1/8 c power-supply rejection 0.3 c/v internal reference ref output voltage 2.48 2.50 2.52 v ref temperature coefficient tc ref 30 p p m / c output resistance 6.5 k ? ref output noise 200 v rms ref power-supply rejection psrr -70 db external reference input ref- input voltage range v ref- 0 500 mv ref+ input voltage range v ref+ 1.0 v dd + 50mv v v ref+ = 2.5v, f sample = 300ksps 40 100 ref+ input current i ref+ v ref+ = 2.5v, f sample = 0 0.1 5 a
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 4 _______________________________________________________________________________________ note 1: tested at v dd = +2.7v, unipolar input mode. note 2: offset nulled. note 3: time for reference to power up and settle to within 1 lsb. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 5: the operational input voltage range for each individual input of a differentially configured pair is from gnd to v dd . the operational input voltage difference is from -v ref /2 to +v ref /2. note 6: see figure 3 (input equivalent circuit) and the typical operating curve in the sampling error vs. source impedance sec- tion. note 7: fast automated test, excludes self-heating effects. note 8: when cnvst is configured as a digital input, do not apply a voltage between v il and v in . note 9: supply current is specified depending on whether an internal or external reference is used for voltage conversions. temperature measurements always use the internal reference. electrical characteristics (continued) (v dd = +2.7v to +3.6v, f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units digital inputs (sclk, din, cs , cnvst) (note 8) input voltage low v il v dd x 0.3 v input voltage high v ih v dd x 0.7 v input hysteresis v hyst 200 mv input leakage current i in v in = 0 or v dd 0.01 1.0 a input capacitance c in 15 pf digital outputs (dout, eoc) i sink = 2ma 0.4 output voltage low v ol i sink = 4ma 0.8 v output voltage high v oh i source = 1.5ma v dd - 0.5 v tri-state leakage current i l cs = v dd 0.05 1 a tri-state output capacitance c out cs = v dd 15 pf power requirements supply voltage v dd 2.7 3.6 v during temp sense 2400 2700 f sample = 300ksps 1750 2000 f sample = 0, ref on 1000 1200 internal reference shutdown 0.2 5 during temp sense 1550 2000 f sample = 300ksps 1050 1200 supply current (note 9) i dd external reference shutdown 0.2 5 a power-supply rejection psr v dd = 2.7v to 3.6v; full-scale input 0.2 1 mv
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units externally clocked conversion 208 sclk clock period t cp data i/o 100 ns sclk duty cycle t ch 40 60 % sclk fall to dout transition t dot c load = 30pf 40 ns cs rise to dout disable t dod c load = 30pf 40 ns cs fall to dout enable t doe c load = 30pf 40 ns din to sclk rise setup t ds 40 ns sclk rise to din hold t dh 0ns c s ri se- to- s c lk ri se s etup ti m et css1 40 ns c s fall-to-sclk hold time t csh0 0ns cksel = 00, cksel = 01 (temp sense) 40 ns cnvst pulse width t csw cksel = 01 (voltage conversion) 1.4 s t t s temp sense 55 voltage conversion 7 cs or cnvst rise to eoc low (note 10) reference power-up 65 s timing characteristics (figure 1) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 integral nonlinearity vs. output code max1227/29/31 toc01 output code integral nonlinearity (lsb) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 differential nonlinearity vs. output code max1227/29/31 toc02 output code differential nonlinearity (lsb) sinad vs. frequency max1227/29/31 toc03 frequency (khz) amplitude (db) 100 10 1 10 20 40 30 60 50 90 80 70 100 0 0.1 1000 typical operating characteristics (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c, unless otherwise noted.) note 10: this time is defined as the number of clock cycles needed for conversion multiplied by the clock period. if the internal ref erence needs to be powered up, the total time is additive. the internal reference is always used for temperature measure ments.
2.4970 2.4974 2.4982 2.4978 2.4986 2.4990 2.7 3.0 3.3 3.6 internal reference voltage vs. supply voltage max1227/29/31 toc10 supply voltage (v) internal reference voltage (v) max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 6 _______________________________________________________________________________________ sfdr vs. frequency max1227/29/31 toc04 frequency (khz) amplitude (db) 100 10 1 20 40 60 80 100 120 0 0.1 1000 supply current vs. sampling rate max1227/29/31 toc05 sampling rate (ksps) supply current ( a) 100 10 300 400 500 600 700 200 1 1000 supply current vs. supply voltage max1227/29/31 toc06 supply voltage (v) supply current ( a) 3.3 3.0 550 600 650 700 500 2.7 3.6 0 0.2 0.1 0.3 0.4 0.5 2.7 3.0 3.3 3.6 shutdown supply current vs. supply voltage max1227/29/31 toc07 supply voltage (v) shutdown supply current ( a) 625 620 615 610 605 -40 10 -15 35 60 85 supply current vs. temperature max1227/29/31 toc08 temperature ( c) supply current ( a) f s = 300ksps 0 0.1 0.2 0.3 0.4 0.5 -40 10 -15 35 60 85 shutdown supply current vs. temperature max1227/29/31 toc09 temperature ( c) shutdown supply current ( a) typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c, unless otherwise noted.)
max1227/max1229/MAX1231 2.510 2.506 2.502 2.498 2.494 2.490 -40 10 -15 35 60 85 internal reference voltage vs. temperature max1227/29/31 toc11 temperature ( c) internal reference voltage (v) -0.3 -0.1 -0.2 0.1 0 0.2 0.3 2.7 3.0 3.3 3.6 offset error vs. supply voltage max1227/29/31 toc12 supply voltage (v) offset error (lsb) -0.3 0 -0.1 -0.2 0.2 0.1 0.3 0.4 -40 10 -15 35 60 85 offset error vs. temperature max1227/29/31 toc13 temperature ( c) offset error (lsb) 0 1.0 0.5 1.5 2.0 gain error vs. supply voltage max1227/29/31 toc14 supply voltage (v) gain error (lsb) 2.7 3.6 3.3 3.0 0 0.5 1.5 1.0 2.0 gain error vs. temperature max1227/29/31 toc15 temperature ( c) gain error (lsb) -40 -15 35 85 60 10 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c, unless otherwise noted.) -1.00 -0.50 0.50 0.25 -0.25 -0.75 0 1.00 0.75 temperature sensor error vs. temperature max1227/29/31 toc16 temperature ( c) temperature sensor error ( c) -40 -15 35 85 60 10 grade b -5 -3 -4 -1 -2 0 1 04 26810 sampling error vs. source impedance max1227/29/31 toc17 source impedance (k ? ) sampling error (lsb)
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 8 _______________________________________________________________________________________ pin description pin MAX1231 tqfn-ep MAX1231 qsop max1229 max1227 name function 2C12, 26, 27, 28, 1C14 ain0C13 analog inputs 1C10 ain0C9 analog inputs 1C6 ain0C5 analog inputs 13 15 ref-/ain14 n eg ati ve inp ut for e xter nal d i ffer enti al refer ence/anal og inp ut 14. see table 3 for details on programming the setup register. 11 ref-/ain10 n eg ati ve inp ut for e xter nal d i ffer enti al refer ence/anal og inp ut 10. see table 3 for details on programming the setup register. 7 ref-/ain6 negative input for external differential reference/analog input 6. see table 3 for details on programming the setup register. 14 16 cnvst / ain15 active-low conversion start input/analog input 15. see table 3 for details on programming the setup register. 12 cnvst / ain11 active-low conversion start input/analog input 11. see table 3 for details on programming the setup register. 8 cnvst / ain7 active-low conversion start input/analog input 7. see table 3 for details on programming the setup register. 15 17 13 9 ref+ positive reference input. bypass to gnd with a 0.1f capacitor. 16 18 14 10 gnd ground 18 19 15 11 v dd power input. bypass to gnd with a 0.1f capacitor. 20 20 16 12 sclk serial clock input. clocks data in and out of the serial interface. (duty cycle must be 40% to 60%.) see table 3 for details on programming the clock mode. 21 21 17 13 cs active-low chip select input. when cs is low, the serial interface is enabled. when cs is high, dout is high impedance. 22 22 18 14 din serial data input. din data is latched into the serial interface on the rising edge of sclk. 23 23 19 15 dout serial data output. data is clocked out on the falling edge of sclk. high impedance when cs is connected to v dd . 24 24 20 16 eoc end of conversion output. data is valid after eoc pulls low. 1, 17, 19, 25 n.c. no connection. not internally connected. ep exposed pad (tqfn only). connect to gnd.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 9 detailed description the max1227/max1229/MAX1231 are low-power, seri- al-output, multichannel adcs with temperature-sensing capability for temperature-control, process-control, and monitoring applications. these 12-bit adcs have inter- nal track and hold (t/h) circuitry that supports single- ended and fully differential inputs. data is converted from an internal temperature sensor or analog voltage sources in a variety of chan nel and data-acquisition configurations. microprocessor (p) control is made easy through a 3-wire spi-/qspi/ microwire-compati- ble serial interface. figure 2 shows a simplified functional diagram of the max1227/max1229/MAX1231 internal architecture. the max1227 has eight single-ended analog input channels or four differential channels. the max1229 has 12 single-ended analog input channels or six differ- ential channels. the MAX1231 has 16 single-ended analog input channels or eight differential channels. sclk din dout cs t dh t doe t ds t ch t css0 t cp t csh1 t csh0 t css1 t dod t dot figure 1. detailed serial-interface timing diagram 12-bit sar adc control serial interface oscillator fifo and accumulator t/h temp sense ref- cnvst sclk cs din eoc dout ain15 ain1 ain2 internal reference ref+ max1227 max1229 MAX1231 figure 2. functional diagram
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 10 ______________________________________________________________________________________ converter operation the max1227/max1229/MAX1231 adcs use a fully dif- ferential, successive-approximation register (sar) con- version technique and an on-chip t/h block to convert temperature and voltage signals into a 12-bit digital result. both single-ended and differential configurations are supported, with a unipolar signal range for single- ended mode and bipolar or unipolar ranges for differ- ential mode. input bandwidth the adcs input-tracking circuitry has a 1mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. anti-alias prefiltering of the input signals is necessary to avoid high-frequen- cy signals aliasing into the frequency band of interest. analog input protection internal esd protection diodes clamp all pins to v dd and gnd, allowing the inputs to swing from (gnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if an off-channel analog input voltage exceeds the supplies, limit the input current to 2ma. 3-wire serial interface the max1227/max1229/MAX1231 feature a serial interface compatible with spi/qspi and microwire devices. for spi/qspi, ensure the cpu serial interface runs in master mode so it generates the serial clock signal. select the sclk frequency of 10mhz or less, and set clock polarity (cpol) and phase (cpha) in the p control registers to the same value. the max1227/ max1229/MAX1231 operate with sclk idling high or low, and thus operate with cpol = cpha = 0 or cpol = cpha = 1. set cs low to latch input data at din on the rising edge of sclk. output data at dout is updated on the falling edge of sclk. bipolar true dif- ferential results and temperature sensor results are available in twos complement format, while all others are in binary. serial communication always begins with an 8-bit input data byte (msb first) loaded from din. use a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see tables 1, 3, 4, and 5). a high-to-low transition on cs ini- tiates the data input operation. the input data byte and the subsequent data bytes are clocked from din into the serial interface on the rising edge of sclk. tables 1C7 detail the register descriptions. bits 5 and 4, cksel1 and cksel0, respectively, control the clock modes in the setup register (see table 3). choose between four different clock modes for various ways to start a conversion and determine whether the acquisi- tions are internally or externally timed. select clock mode 00 to configure cnvst /ain_ to act as a conver- sion start and use it to request the programmed, inter- nally timed conversions without tying up the serial bus. in clock mode 01, use cnvst to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. request and start inter- nally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. use clock mode 11 with sclk up to 4.8mhz for externally timed acquisitions to achieve sampling rates up to 300ksps. clock mode 11 disables scanning and averaging. see figures 4C7 for timing specifica- tions and how to begin a conversion. these devices feature an active-low, end-of-conversion output. eoc goes low when the adc completes the last- requested operation and is waiting for the next input data byte (for clock modes 00 and 10). in clock mode 01, eoc goes low after the adc completes each requested operation. eoc goes high when cs or cnvst goes low. eoc is always high in clock mode 11. single-ended/differential input the max1227/max1229/MAX1231 use a fully differen- tial adc for all conversions. the analog inputs can be configured for either differential or single-ended con- versions by writing to the setup register (see table 3). single-ended conversions are internally referenced to gnd (see figure 3). in differential mode, the t/h samples the difference between two analog inputs, eliminating common-mode dc offsets and noise. in+ and in- are selected from the following pairs: ain0/ain1, ain2/ain3, ain4/ain5, ain6/ain7, ain8/ain9, ain10/ain11, ain12/ain13, and ain14/ain15. ain0Cain7 are available on the max1227, max1229, and MAX1231. ain8Cain11 are only available on the max1229 and MAX1231. ain12Cain15 are only available on the MAX1231. see tables 2C5 for more details on configuring the inputs. for the inputs that can be configured as cnvst or an analog input, only one can be used at a time. for the inputs that can be configured as ref- or an analog input, the ref- configuration excludes the analog input.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 11 unipolar/bipolar address the unipolar and bipolar registers through the setup register (bits 1 and 0). program a pair of analog channels for differential operation by writing a 1 to the appropriate bit of the bipolar or unipolar register. unipolar mode sets the differential input range from 0 to v ref . a negative differential analog input in unipolar mode causes the digital output code to be zero. selecting bipolar mode sets the differential input range to v ref /2. the digital output code is binary in unipolar mode and twos complement in bipolar mode (figures 8 and 9). in single-ended mode, the max1227/max1229/ MAX1231 always operate in unipolar mode. the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . true differential analog input t/h the equivalent circuit of figure 3 shows the max1227/ max1229/MAX1231s input architecture. in track mode, a positive input capacitor is connected to ain0Cain15 in single-ended mode (and ain0, ain2, ain4ain14 in differential mode). a negative input capacitor is con- nected to gnd in single-ended mode (or ain1, ain3, ain5ain15 in differential mode). for external t/h timing, use clock mode 01. after the t/h enters hold mode, the difference between the sampled positive and negative input voltages is converted. the time required for the t/h to acquire an input signal is deter- mined by how quickly its input capacitance is charged. if the input signals source impedance is high, the required acquisition time lengthens. the acquisition time, t acq , is the maximum time needed for a signal to be acquired, plus the power-up time. it is calculated by the following equation: where r in = 1.5k ? , r s is the source impedance of the input signal, and t pwr = 1s, the power-up time of the device. the varying power-up times are detailed in the explanation of the clock mode conversions. t acq is never less than 1.4s, and any source imped- ance below 300 ? does not significantly affect the adcs ac performance. a high-impedance source can be accommodated either by lengthening t acq or by placing a 1f capacitor between the positive and neg- ative analog inputs. internal fifo the max1227/max1229/MAX1231 contain a fifo buffer that can hold up to 16 adc results plus one tem- perature result. this allows the adc to handle multiple internally clocked conversions and a temperature mea- surement, without tying up the serial bus. if the fifo is filled and further conversions are request- ed without reading from the fifo, the oldest adc results are overwritten by the new adc results. each result contains 2 bytes, with the msb preceded by four leading zeros. after each falling edge of cs , the oldest available byte of data is available at dout, msb first. when the fifo is empty, dout is zero. the first 2 bytes of data read out after a temperature measurement always contain the temperature result preceded by four leading zeros, msb first. if another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. temperature results are in degrees celsius (twos complement) at a resolution of 1/8 of a degree. see the temperature measurements section for details on converting the digital code to a temperature. internal clock the max1227/max1229/MAX1231 operate from an internal oscillator, which is accurate within 10% of the 4.4mhz nominal clock rate. the internal oscillator is active in clock modes 00, 01, and 10. read out the data at clock speeds up to 10mhz. see figures 4C7 for details on timing specifications and starting a conversion. txrrxpft acq s in pwr =+ + () 924 + - hold cin+ ref gnd dac cin- v dd /2 comparator ain0-ain15 (single ended); ain0, ain2, ain4?in14 (differential) gnd (single ended); ain1, ain3, ain5?in15 (differential) hold hold figure 3. equivalent input circuit
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 12 ______________________________________________________________________________________ applications information register descriptions the max1227/max1229/MAX1231 communicate between the internal registers and the external circuitry through the spi-/qspi-compatible serial interface. table 1 details the registers and the bit names. tables 2C7 show the various functions within the conversion register, setup register, averaging register, reset regis- ter, unipolar register, and bipolar register. conversion time calculations the conversion time for each scan is based on a num- ber of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external refer- ence is in use. use the following formula to calculate the total conver- sion time for an internally timed conversion in clock modes 00 and 10 (see the electrical characteristics section as applicable): total conversion time = t cnv x n avg x n result + t t s + t rp where: t cnv = t acq (max) + t conv (max) n avg = samples per result (amount of averaging) n result = number of fifo results requested; determined by number of channels being scanned or by nscan1, nscan0 t ts = time required for temperature measurement; set to zero if temp measurement is not requested t rp = internal reference wake up; set to zero if internal reference is already powered up or external reference is being used in clock mode 01, the total conversion time depends on how long cnvst is held low or high, including any time required to turn on the internal reference. conversion time in externally clocked mode (cksel1, cksel0 = 11) depends on the sclk period and how long cs is held high between each set of eight sclk cycles. in clock mode 01, the total conversion time does not include the time required to turn on the internal reference. conversion register select active analog input channels, scan modes, and a single temperature measurement per scan by writing to the conversion register. table 2 details channel selection, the four scan modes, and how to request a temperature measurement. request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the cnvst pin when in clock mode 00 or 01. a conversion is not performed if it is requested on a channel that has been configured as cnvst or ref-. do not request conversions on channels 8C15 on the max1227 and channels 12C15 on the max1229. set chsel3:chselo to the lower channels binary value. if the last two channels are configured as a differential pair and one of them has been reconfigured as cnvst or ref-, the pair is ignored. select scan mode 00 or 01 to return one result per sin- gle-ended channel and one result per differential pair within the requested range, plus one temperature result if selected. select scan mode 10 to scan a single input channel numerous times, depending on nscan1 and nscan0 in the averaging register (table 6). select scan mode 11 to return only one result from a single channel. setup register write a byte to the setup register to configure the clock, reference, and power-down modes. table 3 details the register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 conversion 1 chsel3 chsel2 chsel1 chsel0 scan1 scan0 temp setup 0 1 cksel1 cksel0 refsel1 refsel0 diffsel1 diffsel0 averaging 0 0 1 avgon navg1 navg0 nscan1 nscan0 reset 0001 reset xxx unipolar mode (setup) uch0/1 uch2/3 uch4/5 uch6/7 uch8/9* uch10/11 uch12/138** uch14/15** bipolar mode (setup) bch0/1 bch1/2 bch4/5 bch6/7 bch8/9* bch10/11 bch12/13** bch14/15** table 1. input data byte (msb first) *unipolar/bipolar channels 8C15 are only valid on the max1229 and MAX1231. *unipolar/bipolar channels 12C15 are only valid on the MAX1231. x = dont care.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 13 bits in the setup register. bits 5 and 4 (cksel1 and cksel0) control the clock mode, acquisition and sam- pling, and the conversion start. bits 3 and 2 (refsel1 and refsel0) control internal or external reference use. bits 1 and 0 (diffsel1 and diffsel0) address the unipolar mode and bipolar mode registers and configure the analog input channels for differential operation. unipolar/bipolar registers the final 2 bits (lsbs) of the setup register control the unipolar/bipolar mode address registers. set bits 1 and 0 (diffsel1 and diffsel0) to 10 to write to the unipo- lar mode register. set bits 1 and 0 to 11 to write to the bipolar mode register. in both cases, the setup byte must be followed immediately by 1 byte of data written to the unipolar register or bipolar register. hold cs low and run 16 sclk cycles before pulling cs high. if the last 2 bits of the setup register are 00 or 01, neither the unipolar mode register nor the bipolar mode register is written. any subsequent byte is recognized as a new input data byte. see tables 4 and 5 to program the unipolar and bipolar mode registers. if a channel is configured as both unipolar and bipolar, the unipolar setting takes precedence. in unipolar mode, ain+ can exceed ain- by up to v ref . the out- put format in unipolar mode is binary. in bipolar mode, either input can exceed the other by up to v ref /2. the output format in bipolar mode is two's complement. averaging register write to the averaging register to configure the adc to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. table 2 details the four scan modes available in the con- version register. all four scan modes allow averaging as long as the avgon bit, bit 4 in the averaging register, is set to 1. select scan mode 10 to scan the same channel multiple times. clock mode 11 disables averaging. reset register write to the reset register (as shown in table 7) to clear the fifo or to reset all registers to their default states. set the reset bit to 1 to reset the fifo. set the reset bit to zero to return the max1227/max1229/MAX1231 to the default power-up state. power-up default state the max1227/max1229/MAX1231 power up with all blocks in shutdown, including the reference. all registers power up in state 00000000, except for the setup regis- ter, which powers up in clock mode 10 (cksel1 = 1). bit name bit function 7 (msb) set to 1 to select conversion register. chsel3 6 analog input channel select. chsel2 5 analog input channel select. chsel1 4 analog input channel select. chsel0 3 analog input channel select. scan1 2 scan mode select. scan0 1 scan mode select. temp 0 (lsb) set to 1 to take a single temperature measurement. the first conversion result of a scan contains temperature information. table 2. conversion register * see below for bit details. chsel3 chsel2 chsel1 chsel0 selected channel (n) 0 0 0 0 ain0 0 0 0 1 ain1 0 0 1 0 ain2 0 0 1 1 ain3 0 1 0 0 ain4 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 ain7 1 0 0 0 ain8 1 0 0 1 ain9 1 0 1 0 ain10 1 0 1 1 ain11 1 1 0 0 ain12 1 1 0 1 ain13 1 1 1 0 ain14 1 1 1 1 ain15 scan1 scan0 scan mode (channel n is selected by bits chsel3?hsel0) 0 0 scans channels 0 through n. 01 scans channels n through the highest numbered channel. 10 s cans channel n r ep eated l y. the aver ag i ng r eg i ster sets the num b er of r esul ts. 1 1 no scan. converts channel n once only.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 14 ______________________________________________________________________________________ table 3. setup register bit name bit function 7 (msb) set to zero to select setup register. 6 set to 1 to select setup register. cksel1 5 clock mode and cnvst configuration. resets to 1 at power-up. cksel0 4 clock mode and cnvst configuration. refsel1 3 reference mode configuration. refsel0 2 reference mode configuration. diffsel1 1 unipolar/bipolar mode register configuration for differential mode. diffsel0 0 (lsb) unipolar/bipolar mode register configuration for differential mode. cksel1 cksel0 conversion clock acquisition/sampling cnvst configuration 0 0 internal internally timed cnvst 0 1 internal externally timed through cnvst cnvst 1 0 internal internally timed ain15/11/7 1 1 external (4.8mhz max) externally timed through sclk ain15/11/7 refsel1 refsel0 voltage reference autoshutdown ref- configuration 0 0 internal reference off after scan; need wake-up delay. ain14/10/6 0 1 external single ended reference off; no wake-up delay. ain14/10/6 1 0 internal reference always on; no wake-up delay. ain14/10/6 1 1 external differential reference off; no wake-up delay. ref- diffsel1 diffsel0 function 0 0 no data follows the setup byte. unipolar mode and bipolar mode registers remain unchanged. 0 1 no data follows the setup byte. unipolar mode and bipolar mode registers remain unchanged. 1 0 one byte of data follows the setup byte and is written to the unipolar mode register. 1 1 one byte of data follows the setup byte and is written to the bipolar mode register. * see below for bit details.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 15 temperature measurements the max1227/max1229/MAX1231 perform tempera- ture measurements with an internal diode-connected transistor. the diode bias current changes from 68a to 4a to produce a temperature-dependent bias volt- age difference. the second conversion result at 4a is subtracted from the first at 68a to calculate a digital value that is proportional to absolute temperature. the output data appearing at dout is the above digital code minus an offset to adjust from kelvin to celsius. the reference voltage used for the temperature mea- surements is derived from the internal reference source to ensure that 1 lsb corresponds to 1/8 of a degree. output data format figures 4C7 illustrate the conversion timing for the max1227/max1229/MAX1231. the 12-bit conversion result is output in msb-first format with four leading zeros. din data is latched into the serial interface on the rising edge of sclk. data on dout transitions on the falling edge of sclk. conversions in clock modes 00 and 01 are initiated by cnvst . conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. data is binary for unipo- lar mode and twos complement for bipolar mode. bit name bit function uch0/1 7 (msb) set to 1 to configure ain0 and ain1 for unipolar differential conversion. uch2/3 6 set to 1 to configure ain2 and ain3 for unipolar differential conversion. uch4/5 5 set to 1 to configure ain4 and ain5 for unipolar differential conversion. uch6/7 4 set to 1 to configure ain6 and ain7 for unipolar differential conversion. uch8/9 3 set to 1 to configure ain8 and ain9 for unipolar differential conversion (max1229/MAX1231 only). uch10/11 2 set to 1 to configure ain10 and ain11 for unipolar differential conversion (max1229/MAX1231 only). uch12/13 1 set to 1 to configure ain12 and ain13 for unipolar differential conversion (MAX1231 only). uch14/15 0 (lsb) set to 1 to configure ain14 and ain15 for unipolar differential conversion (MAX1231 only). table 4. unipolar mode register (addressed through setup register) bit name bit function bch0/1 7 (msb) set to 1 to configure ain0 and ain1 for bipolar differential conversion. bch2/3 6 set to 1 to configure ain2 and ain3 for bipolar differential conversion. bch4/5 5 set to 1 to configure ain4 and ain5 for bipolar differential conversion. bch6/7 4 set to 1 to configure ain6 and ain7 for bipolar differential conversion. bch8/9 3 set to 1 to configure ain8 and ain9 for bipolar differential conversion (max1229/MAX1231 only). bch10/11 2 set to 1 to configure ain10 and ain11 for bipolar differential conversion (max1229/MAX1231 only). bch12/13 1 set to 1 to configure ain12 and ain13 for bipolar differential conversion (MAX1231 only). bch14/15 0 (lsb) set to 1 to configure ain14 and ain15 for bipolar differential conversion (MAX1231only). table 5. bipolar mode register (addressed through setup register)
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 16 ______________________________________________________________________________________ bit name bit function 7 (msb) set to zero to select averaging register. 6 set to zero to select averaging register. 5 set to 1 to select averaging register. avgon 4 set to 1 to turn averaging on. set to zero to turn averaging off. navg1 3 configures the number of conversions for single-channel scans. navg0 2 configures the number of conversions for single-channel scans. nscan1 1 single-channel scan count. (scan mode 10 only.) nscan0 0 (lsb) single-channel scan count. (scan mode 10 only.) table 6. averaging register avgon navg1 navg0 function 0 x x performs 1 conversion for each requested result. 1 0 0 performs 4 conversions and returns the average for each requested result. 1 0 1 performs 8 conversions and returns the average for each requested result. 1 1 0 performs 16 conversions and returns the average for each requested result. 1 1 1 performs 32 conversions and returns the average for each requested result. nscan1 nscan0 function (applies only if scan mode 10 is selected) 0 0 scans channel n and returns 4 results. 0 1 scans channel n and returns 8 results. 1 0 scans channel n and returns 12 results. 1 1 scans channel n and returns 16 results. bit name bit function 7 (msb) set to zero to select reset register. 6 set to zero to select reset register. 5 set to zero to select reset register. 4 set to 1 to select reset register. reset 3 set to zero to reset all registers. set to 1 to clear the fifo only. x 2 reserved. dont care. x 1 reserved. dont care. x 0 (lsb) reserved. dont care. table 7. reset register see below for bit details.
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 17 internally timed acquisitions and conversions using cnvst performing conversions in clock mode 00 in clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through cnvst and performed automatically using the internal oscilla- tor. results are added to the internal fifo to be read out later. see figure 4 for clock mode 00 timing. initiate a scan by setting cnvst low for at least 40ns before pulling it high again. the max1227/max1229/ MAX1231 then wake up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. wait until eoc goes low before pulling cs low to communicate with the serial interface. eoc stays low until cs or cnvst is pulled low again. a temperature measurement result, if requested, pre- cedes all other fifo results. do not initiate a second cnvst before eoc goes low; otherwise, the fifo can become corrupted. externally timed acquisitions and internally timed conversions with cnvst performing conversions in clock mode 01 in clock mode 01, conversions are requested one at a time using cnvst and performed automatically using the internal oscillator. see figure 5 for clock mode 01 timing. setting cnvst low begins an acquisition, wakes up the adc, and places it in track mode. hold cnvst low for at least 1.4s to complete the acquisition. if internal ref- erence needs to wake up, an additional 65s is required for the internal reference to power up. if a tem- perature measurement is being requested, reference power-up and temperature measurement are internally timed. in this case, hold cnvst low for at least 40ns. set cnvst high to begin a conversion. after the con- version is complete, the adc shuts down and pulls eoc low. eoc stays low until cs or cnvst is pulled low again. wait until eoc goes low before pulling cs or cnvst low. if averaging is turned on, multiple cnvst pulses need to be performed before a result is written to the fifo. once the proper number of conversions has been per- formed to generate an averaged fifo result, as speci- fied by the averaging register, the scan logic automatically switches the analog input multiplexer to the next-requested channel. if a temperature measure- ment is programmed, it is performed after the first rising edge of cnvst following the input data byte written to the conversion register. the result is available on dout once eoc has been pulled low. (up to 514 internally clocked acquisitions and conversions) cs dout msb1 lsb1 msb2 sclk cnvst eoc set cnvst low for at least 40ns to begin a conversion. figure 4. clock mode 00
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference 18 ______________________________________________________________________________________ internally timed acquisitions and conversions using the serial interface performing conversions in clock mode 10 in clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are per- formed automatically using the internal oscillator. this is the default clock mode upon power-up. see figure 6 for clock mode 10 timing. initiate a scan by writing a byte to the conversion regis- ter. the max1227/max1229/MAX1231 then power up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. if a temperature measurement is requested, the tempera- ture result precedes all other fifo results. eoc stays low until cs is pulled low again. cs dout sclk cnvst eoc (conversion2) msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) request multiple conversions by setting cnvst low for each conversion. figure 5. clock mode 01 (up to 514 internally clocked acquisitions and conversions) msb1 lsb1 msb2 (conversion byte) cs dout sclk din eoc the conversion byte begins the acquisition. cnvst is not required. figure 6. clock mode 10
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 19 externally clocked acquisitions and conversions using the serial interface performing conversions in clock mode 11 in clock mode 11, acquisitions and conversions are ini- tiated by writing to the conversion register and are per- formed one at a time using the sclk as the conversion clock. scanning and averaging are disabled, and the conversion result is available at dout during the con- version. see figure 7 for clock mode 11 timing. initiate a conversion by writing a byte to the conversion register followed by 16 sclk cycles. if cs is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100s. to continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. if reference mode 00 is requested, or if an external ref- erence is selected but a temperature measurement is being requested, wait 65s with cs high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. to perform a tem- perature measurement, write 24 bytes (192 cycles) of zeros after the conversion byte. the temperature result appears on dout during the last 2 bytes of the 192 cycles. partial reads and partial writes if the first byte of an entry in the fifo is partially read ( cs is pulled high after fewer than eight sclk cycles), the second byte of data that is read out contains the next 8 bits (not b7Cb0). the remaining bits are lost for that entry. if the first byte of an entry in the fifo is read out fully, but the second byte is read out partially, the rest of the entry is lost. the remaining data in the fifo is uncorrupted and can be read out normally after tak- ing cs low again, as long as the 4 leading bits (normal- ly zeros) are ignored. internal registers that are written partially through the spi contain new values, starting at the msb up to the point that the partial write is stopped. the part of the register that is not written contains previ- ously written values. if cs is pulled low before eoc goes low, a conversion cannot be completed and the fifo is corrupted. transfer function figure 8 shows the unipolar transfer function for single- ended or differential inputs. figure 9 shows the bipolar transfer function for differential inputs. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = v ref / 2.5v for unipolar and bipolar operation, and 1 lsb = 0.125c for temperature measurements. layout, grounding, and bypassing for best performance, use pc boards. do not use wire- wrap boards. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the max1227/max1229/MAX1231 package. high-frequen- cy noise in the v dd power supply can affect perfor- mance. bypass the v dd supply with a 0.1f capacitor to gnd, close to the v dd pin. minimize capacitor lead lengths for best supply-noise rejection. if the power sup- ply is very noisy, connect a 10 ? resistor in series with the supply to improve power-supply filtering. for the tqfn package, connect its exposed pad to ground. cs dout sclk din eoc msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) (conversion byte) externally timed acquisition, sampling and conversion without cnvst. figure 7. clock mode 11
max1227/max1229/MAX1231 definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max1227/max1229/MAX1231 is measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys rms amplitude to the rms equivalent of all other adc output signals: sinad (db) = 20 x log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantiza- tion noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 12-bit 300ksps adcs with fifo, temp sensor, internal reference 20 ______________________________________________________________________________________ figure 9. bipolar transfer function, full scale (fs) = v ref / 2 output code full-scale transition 11 . . . . . . 111 11 . . . . . . 110 11 . . . . . . 101 00 . . . . . . 011 00 . . . . . . 010 00 . . . . . . 001 00 . . . . . . 000 123 0 (com) fs fs - 3/2 lsb fs = v ref + v com zs = v com input voltage (lsb) 1 lsb = v ref 4096 011 . . . . . . 111 011 . . . . . . 110 000 . . . . . . 010 000 . . . . . . 001 000 . . . . . . 000 111 . . . . . . 111 111 . . . . . . 110 111 . . . . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1 lsb *v com v ref / 2 + v com + v com fs = v ref 2 -fs = -v ref 2 1 lsb = v ref 4096 figure 8. unipolar transfer function, full scale (fs) = v ref
total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v2Cv5 are the amplitudes of the first five harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest distor- tion component. chip information process: bicmos log / thd x v v v v v =+++ ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference ______________________________________________________________________________________ 21 ordering information (continued) 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 eoc dout din cs ain3 ain2 ain1 ain0 top view sclk v dd gnd ref+ ain7 ain6 ain5 ain4 16 15 14 13 9 10 11 12 cnvst/ain15 ref-/ain14 ain13 ain12 ain11 ain10 ain9 ain8 qsop MAX1231 28 27 26 25 24 23 22 8 9 10 11 12 13 14 ain9 ain2 ain1 ain0 n.c. eoc dout din ain10 ain11 ain12 ain13 ref-/ain14 cnvst/ain15 15 16 17 18 19 20 21 ref+ gnd n.c. v dd n.c. sclk cs 7 6 5 4 3 2 1 ain8 ain7 ain6 ain5 ain4 ain3 n.c. MAX1231 tqfn + + pin configurations (continued) *ep = exposed pad. (connect to gnd.) + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package MAX1231 bceg+ 0c to +70c 24 qsop MAX1231beeg+ -40c to +85c 24 qsop MAX1231bcti+ 0c to +70c 28 tqfn-ep* MAX1231beti+ -40c to +85c 28 tqfn-ep* package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 qsop e16+1 21-0055 90-0167 20 qsop e20+1 21-0055 90-0168 24 qsop e24+1 21-0055 90-0172 28 tqfn-ep t2855+6 21-0140 90-0026
max1227/max1229/MAX1231 12-bit 300ksps adcs with fifo, temp sensor, internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 2/10 removed the a grade products from the ordering information table and electrical characteristics table. 1, 3, 21 4 8/10 added lead-free information to ordering information and package information sections 1, 21 5 12/10 changed several data sheet specifications 1C5, 7, 9, 21 6 5/11 revised ordering information 1 7 4/12 corrected error in acquisition time formula 11

▲Up To Search▲

Price & Availability of MAX1231

	To Download MAX1231 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .